SPI至I2C桥的FPGA实现FPGA Implementation Of SPI To I2C Bridge

作者: Abhilash S.Warrier VLSI Design VNIT Nagpur Akshay S.Belvadi VLSI Design VNIT Nagpur Dhiraj R.Gawhane VLSI Design VNIT Nagpur Babu Ravi Teja K VLSI Design VNIT Nagpur

Abstract

Today’s electronic system is not a standalone unit instead working in a group, where each IC communicates with each other very frequently, it is necessary to have an efficient simple protocol for effective communication among these components, the major area being serial communication. SPI and I2C are two widely accepted and practised global standards for both inter-chip and intra-chip serial communication for low/medium bandwidth. The paper discusses the two protocols in detail and a SPI to I2C Bridge. Design and FPGA implementation of this bridge is in conformity with design reuse methodology.

当今的电子系统不是一个独立的单元,而是成组工作的,每个IC之间的通信非常频繁,必须有一个有效的简单协议来实现这些组件之间的有效通信,主要领域是串行通信。 SPI和I2C是针对低/中带宽的芯片间和芯片内串行通信的两个广泛接受和实践的全球标准。 本文详细讨论了这两种协议以及SPI至I2C桥。 该桥的设计和FPGA实现与设计重用方法一致。

Key words- I2C, SPI, SPI to I2C bridge, FPGA.

1. Introduction

For low end low/medium bandwidth serial communication the two worldwide accepted standards are SPI and I2C. The two protocols have their own prospects and are strong competitors to each other. A comparative study of the two protocols is discussed in [3]. By and large there is a high probability that they coexist in the digital world. With a lot of peripheral devices from a variety of vendors there is always a choice to be made between the two. The major emphasis of the paper is to implement a SPI to I2C Bridge through which there can be a seamless communication between the I2C SLAVE and the SPI MASTER. However, there is a large area overhead involved in this process. The paper initially discusses the major aspects about the I2C and SPI protocols. The detailed explanation of SPI and I2C and their specifications can be found in [7] and [6] respectively. The later part explains the SPI to I2C Bridge modelled as a FSM.

对于低端低/中带宽串行通信,两个全球公认的标准是SPI和I2C。 两种协议都有各自的前景,并且彼此之间是强大的竞争者。 在[3]中讨论了两种协议的比较研究。 总的来说,它们很可能共存于数字世界。 有了来自不同供应商的大量外围设备,总是可以在两者之间做出选择。 本文的主要重点是实现SPI至I2C桥接器,通过该桥接器可以在I2C SLAVE和SPI MASTER之间实现无缝通信。 但是,此过程涉及大面积的开销。 本文首先讨论了有关I2C和SPI协议的主要方面。 SPI和I2C及其规格的详细说明分别可以在[7]和[6]中找到。 下一部分将说明建模为FSM的SPI至I2C桥。

2. Inter Integrated Circuit (I2C)

I2C is a serial, short range low level communication protocol with multi master capability. It is the simplest of its kind with only two external world connections viz. SDA (Serial Data) and SCL (Serial Clock) line. The three modes of operation of I2C are: a. Standard mode – data transfer up to 100 Kbps b. Fast mode – data transfer up to 400 Kbps c. High Speed mode – data transfer up to 3.4 Mbps. The maximum device driven capability is limited just by the total drivable load capacitance which should not exceed 400pF.

I2C是具有多主机功能的串行,短程低级通信协议。 它是同类中最简单的,只有两个外部世界连接。 SDA(串行数据)和SCL(串行时钟)线。 I2C的三种操作模式是: 标准模式-数据传输速率高达100 Kbps b。 快速模式-数据传输速率高达400 Kbps c。 高速模式-数据传输速率高达3.4 Mbps。 最大的设备驱动能力仅受可驱动负载电容的总和限制,该电容不应超过400pF。

Data transfer takes place via the SDA and SCL lines. Any data transition can occur on SDA line only when the SCL line is on Logic Low and all these transitions have to settle down before the SCL goes to Logic high. I2C is a bit oriented bi-directional protocol there by facilitating a Serial Full Duplex communication between the master and the slave.

数据传输通过SDA和SCL线进行。 仅当SCL线处于逻辑低电平并且SCL变为逻辑高电平之前,所有这些转换都必须稳定下来时,才能在SDA线上发生任何数据转换。 I2C是一种位导向的双向协议,它通过促进主机和从机之间的串行全双工通信来实现。

Since, it is a bit-oriented protocol there are special conditions defined for the START and STOP conditions of the data transmitted on SDA line. START is identified when there is a falling edge (HIGH to LOW) detected on SDA line when SCL is in Logic HIGH state. STOP is identified when there is a rising edge (LOW to HIGH) detected on the SDA line when SCL is in logic HIGH state.

由于这是一个面向位的协议,因此为在SDA线上传输的数据的START和STOP条件定义了特殊条件。 当SCL处于逻辑高电平状态时,如果在SDA线上检测到下降沿(从高到低),则识别为START。 当SCL处于逻辑高电平状态时,如果在SDA线上检测到上升沿(从低到高),则识别为STOP。

There is another special condition in which a START condition is repeated instead of a STOP following a START and it is treated as a Repeated START case which is logically equal to a fresh data transfer state. At any given point of time the I2C bus can be in any of the two states BUSY: A state after START and before STOP. IDLE: A state after STOP and before the next START.

还有另一种特殊条件,其中在启动之后重复启动条件而不是停止,并且将其视为重复启动情况,在逻辑上等于新的数据传输状态。 在任何给定的时间点,I2C总线都可以处于两种状态BUSY:处于START之后和STOP之前的状态。 空闲:STOP之后到下一个START之前的状态。

MASTER is any device that which has control over the SCL line and has the capability to initiate and terminate a data transfer, it can also control the addressing of other devices connected as slaves. SLAVE is just any device which is just capable of sending or receiving data and addressed by a MASTER. I2C allows the master both to transmit as well as receive data to or from a slave. Multi MASTER Mode is also allowed. In such a case an ARBITRATION process takes place to decide which master is going to control the bus.

MASTER是可以控制SCL线路并能够启动和终止数据传输的任何设备,它还可以控制作为从设备连接的其他设备的寻址。 SLAVE就是任何能够发送或接收数据并由MASTER寻址的设备。 I2C允许主机与从机之间传输和接收数据。 也允许使用多重主模式。 在这种情况下,仲裁过程将发生,以决定哪个主机将控制总线。

2.1 Data transfer on I2C

Data Transfer is Byte oriented and the number of data Bytes transmitted per transfer is unrestricted. Data bits are transferred one bit per clock cycle after the START condition. Byte is a combination of eight data bits and an Acknowledgement bit is necessary after every byte. Transmission takes place as MSBF (Most Significant Bit First). Initially MASTER sends the Address of this slave with which it wants to initiate a communication and the further communication depends on the Acknowledgment bit from SLAVE.

数据传输面向字节,并且每次传输传输的数据字节数不受限制。 在开始条件之后,每个时钟周期将数据位传送一位。 字节是八个数据位的组合,每个字节后都需要一个确认位。 传输以MSBF(最高有效位在前)进行。 最初,MASTER发送要与其发起通信的该从站的地址,而进一步的通信则取决于来自SLAVE的确认位。

2.2 Acknowledgement

When the Master has completed 8 data bits transmission, it will let the SDA line be in logic HIGH state. During the next clock pulse if the SLAVE pulls down the SDA line when the SCL is high, then it is an Acknowledgement received from the slave that the data has been received. The Slave can now Hold the SCL Line in Logic Low state which will push the master into Wait state else the master will continue with the next set of data.

当主机完成8个数据位的传输时,它将使SDA线处于逻辑高电平状态。 在下一个时钟脉冲期间,如果在SCL为高电平时从器件将SDA线拉低,则这是从器件接收到的确认,表示已接收到数据。 现在,从机可以将SCL线路保持在逻辑低状态,这会将主设备推入等待状态,否则主设备将继续处理下一组数据。

To give a NACK (Negative Acknowledgement) the slave will simply let the SDA line to remain in its logic HIGH state during the ninth clock pulse. The Master in such a case will generate either a STOP or a Repeated Start condition. In case, if the MASTER is acting as a receiver for a slave transmitter, the MASTER signals the end of data transmission by not acknowledging the last Byte of the data stream. The slave releases the SDA line and MASTER can now generate a STOP or Repeated Start condition.

为了给出NACK(否定应答),从器件将在第九个时钟脉冲期间简单地使SDA线保持其逻辑高电平状态。 在这种情况下,主机将产生“停止”或“重复启动”条件。 如果MASTER充当从属发送器的接收器,则MASTER通过不确认数据流的最后一个字节来发信号通知数据传输结束。 从机释放SDA线,MASTER现在可以生成STOP或Repeated Start条件。

2.3 Arbitration

I2C being Multi-Master capable, has a welldefined Arbitration process. Any Master which wants to transmit data will search for the availability of a free SDA line, if one or more masters have data to be sent. They generate the START bit at the same instant and now there is a resource conflict. The master which is trying to drive the SDA line will sample the value of SDA and compares it with what it has to send. If they match it continues to transmit, else it has lost the arbitration process for that Byte transfer period and may generate clock pulses on SCL till the end of that Byte period. If the losing master has a slave mode too then it immediately switches to its slave mode.

I2C具有多主机功能,具有定义明确的仲裁流程。 如果一个或多个主机要发送数据,则任何要传输数据的主机都将搜索一条免费的SDA线路。 它们在同一时刻生成START位,现在存在资源冲突。 试图驱动SDA线的主机将采样SDA的值,并将其与发送的值进行比较。 如果它们匹配,它将继续发送,否则它将丢失该字节传输周期的仲裁过程,并可能在SCL上生成时钟脉冲,直到该字节周期的结尾。 如果丢失的主机也具有从机模式,那么它将立即切换到其从机模式。

Since, the first ever transmission is the address of the slave with which the connection is to be established and both the masters want to communicate with the same Slave, then the arbitration continues. Arbitration takes place on the data bits if the master is the Transmitter or on Acknowledge bits if the master is working as a receiver. Since the data on the SDA line is the same as that of the winning MASTER, ideally no data is lost during the Arbitration process. Arbitration is only for masters and slaves can‟t take part in it.

由于第一个传输是要与之建立连接的从站的地址,并且两个主站都希望与同一从站进行通信,因此仲裁将继续。 如果主机是发送器,则在数据位上进行仲裁;如果主机是接收器,则在确认位上进行仲裁。 由于SDA线上的数据与获胜的MASTER的数据相同,因此理想情况下,仲裁过程中不会丢失任何数据。 仲裁仅适用于主机,从机不能参与。

2.4 Synchronization

All the Masters can generate its own clock but for a bit by bit arbitration process it is necessary to have a well-defined clock. For all the devices that are willing to communicate via the SDA of I2C, their clock signals are wired together and the SCL will be in LOW state for duration equal to the Maximum Clock LOW period and will be in logic HIGH for a duration which is the minimum Clock HIGH.

所有的主机都可以生成自己的时钟,但是对于逐位仲裁过程来说,必须有一个定义明确的时钟。 对于所有愿意通过I2C的SDA进行通信的设备,它们的时钟信号连接在一起,并且SCL处于低电平状态的持续时间等于最大时钟低电平周期,并且处于逻辑高电平的持续时间为 最小时钟高电平。

2.5 Frame format

The I2C connected devices are capable of two way communication with their slave. The MASTER can either act as a transmitter or a receiver, in the sense that it can either write data to a slave or read data from the slave. Every slave connected to the bus has a unique address in a 7 bit address format. The eighth bit of the first transmitted byte will tell whether the MASTER is going to work as a Transmitter or a Receiver. If eighth bit is a zero it says that MASTER is transmitter else it‟s a receiver.

与I2C连接的设备能够与其从设备进行双向通信。 MASTER既可以充当发送器也可以充当接收器,因为它既可以将数据写入从设备,也可以从从设备读取数据。 连接到总线的每个从站都有一个7位地址格式的唯一地址。 发送的第一个字节的第八位将告诉主机是否将用作发送器或接收器。 如果第八位为零,则表示MASTER为发送器,否则为接收器。

3. Serial Peripheral Interface (SPI)

SPI facilitates a Synchronous, Duplex and Serial Communication between the Peripherals. It supports up to 400 Mbps Data transfer speed between various peripherals and the Microprocessor. Similar to its counterpart SPI also provides a simple interface with only four pins to the external world MISO, MOSI, SCLK and SSN.

SPI促进了外围设备之间的同步,双工和串行通信。 它支持各种外设与微处理器之间的数据传输速度高达400 Mbps。 与其类似的SPI相似,SPI还提供了一个简单的接口,该接口只有四个引脚可以连接到外部世界MISO,MOSI,SCLK和SSN。

3.1 Pin description

SCLK: Serial Clock line used to synchronize the data transfer. Master only can generate the Clock.

SCLK:串行时钟线,用于同步数据传输。 只有Master可以生成时钟。

MISO: Master In Slave Out also referred as Serial Data Input (SDI) line used to send data to the master from a slave.

MISO:主机输入从机输出也称为串行数据输入(SDI)线,用于从从机发送数据到主机。

MOSI: Master Out Slave In also referred as Serial Data out (SDO) line used to send the data from master to slave.

MOSI:主机输出从机输入,也称为串行数据输出(SDO)线,用于将数据从主机发送到从机。

SSN: Slave Select signal which is active low line and for each device connected on the bus the master dedicates a special line for each slave entity. So to drive „n‟ no. of slaves on the bus master should have „n‟ SSN lines.

SSN:从选择信号,它是低电平有效线路,对于总线上连接的每个设备,主机都为每个从机实体分配一条专用线路。 因此要驱动“ n”号。 总线主站上的从站中的几条应具有“ n”条SSN线。

3.2 SPI registers

There are various internal registers in the SPI they are as follows in the increasing order of their addresses: SPI Control Register 1, SPI Control Register 2, SPI Baud Rate Register, SPI Status Register and SPI Data Register. The Detailed Description of these registers is discussed elsewhere [7].

SPI中有各种内部寄存器,它们按照其地址的升序排列如下:SPI控制寄存器1,SPI控制寄存器2,SPI波特率寄存器,SPI状态寄存器和SPI数据寄存器。 这些寄存器的详细描述在其他地方讨论[7]。

3.3 Data transfer

Data Transfer between MASTER and SLAVE takes place with the help of a SPI Data Register. This Register is connected as a shift register and is connected to MOSI pin in MASTER and MISO pin in the slave. The data is clocked in and out of the register in FIFO format. When a Device is not selected it has to Tri-state the MISO line. There is an option of multiple receivers by Buffering but multiple transmitters is not allowed because there will be contention problem on the Bus.

MASTER和SLAVE之间的数据传输借助SPI数据寄存器进行。 该寄存器作为移位寄存器连接,并连接到MASTER的MOSI引脚和从器件的MISO引脚。 数据以FIFO格式移入和移出寄存器。 未选择设备时,必须将MISO线置于三态。 可以通过缓冲选择多个接收器,但不允许多个发送器,因为总线上会出现争用问题。

3.4 Synchronization

During SPI transmission Data is handled serially at both the master and slave sides. The SCLK line supervises the data transfer on both the data lines. SPI Control register 1 has two bits CPOL and CPHA which will decide whether the clock signal is an active HIGH or Active LOW signal and on which edge the data transfer takes place. CPHA = „0‟ indicates the data is to be sampled on Leading edge and CPHA=‟1‟ Indicates Data is to be sampled on trailing edge. Both the MATER and SLAVE are to be initialized with the same values for communication.

在SPI传输期间,数据在主机和从机端都进行串行处理。 SCLK线监控两条数据线上的数据传输。 SPI控制寄存器1具有两个CPOL和CPHA位,这两个位将决定时钟信号是有效的高电平还是有效的低电平信号,并确定在哪个边沿进行数据传输。 CPHA =“ 0”表示要在上升沿采样,CPHA =“ 1”表示要在下降沿采样。 MATER和SLAVE都将使用相同的值进行初始化以进行通信

4. SPI to I2C Bridge

The SPI MASTER which wants to drive the I2C slave does so via the interface module. It includes a SPI SLAVE directly driven by its MASTER and our SPI to I2C Bridge interfaces SPI SLAVE and the I2C MASTER which in turn drives its SLAVE as shown in fig.7. The designed SPI to I2C Bridge acts a converter and bridges the SPI slave to an I2C master. The state diagram of the device is shown in fig. 8.

想要驱动I2C从器件的SPI MASTER通过接口模块来实现。 它包括一个由其MASTER直接驱动的SPI SLAVE,以及我们的SPI至I2C桥接口SPI SLAVE和I2C MASTER,后者又驱动其SLAVE,如图7所示。 设计的SPI至I2C桥接器充当一个转换器,并将SPI从器件桥接至I2C主器件。 设备的状态图如图2所示。 8。

The SPI to I2C Bridge waits in READY state and continues to be in that state as long as spi_busy is HIGH or spi_ready is LOW. If there is an event which makes spi_busy LOW (saying that the SPI slave is not busy) and spi_ready HIGH (which indicates a new data arrival from the SPI master) then it receives data from the SPI Slave thereby entering into SPI_RX state. Then SPI data is latched.

SPI至I2C桥接器在READY状态下等待,并且只要spi_busy为高或spi_ready为低,便继续处于该状态。 如果发生事件使spi_busy变为低电平(表明SPI从机不忙)并且spi_ready变为高电平(表示来自SPI主设备的新数据),则它将从SPI从设备接收数据,从而进入SPI_RX状态。 然后锁存SPI数据。

Then it checks for a I2C transaction enable bit which is 25th bit of received data and if it is HIGH it proceeds to the next state the I2C state else it will get back to the READY state .When in I2C state it waits for the I2C data transfer to be finished. If the SPI is not busy then it again moves to the ready state after writing the I2C transaction to the slave-transmission-register.

然后它检查一个I2C事务使能位,它是接收到的数据的第25位,如果它为高电平,则进入下一个状态,即I2C状态,否则将返回到READY状态。当处于I2C状态时,它等待I2C数据。 转移完成。 如果SPI不忙,则在将I2C事务写入从发送寄存器后,它将再次进入就绪状态。

5. Results and discussion

The designed SPI to I2C Bridge has been coded using VHDL and simulated using Model-sim SE 6.2b. Synthesis is done using Xilinx ISE Design suite 14.2 and implemented on Spartan 3E FPGA.

设计的SPI至I2C桥已经使用VHDL进行了编码,并使用Model-sim SE 6.2b进行了仿真。 综合使用Xilinx ISE设计套件14.2完成,并在Spartan 3E FPGA上实现。

6. Conclusions and future scope

The paper has shown FPGA implementation of SPI to I2C Bridge. This enables I2C slaves to be driven by SPI master. This will introduce a large area over head with the bridge consuming more area than the I2C and SPI itself .So power area optimization of this bridge is a challenge for the designers.

本文显示了SPI至I2C桥的FPGA实现。 这使I2C从器件可以由SPI主器件驱动。 这将导致大面积的开销,导致桥比I2C和SPI本身消耗更多的面积。因此,优化桥的功率区域对设计人员来说是一个挑战。

Reference

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